(1) Field of the Invention
The present invention relates to semiconductor memory devices such as dynamic random access memories (DRAMs), static RAMs (SRAMs), flash memories, MRAMs, PRAMs, and ReRAMs.
(2) Disclosure of the Prior Art
One of known conventional semiconductor memory devices is a DRAM with a so-called hierarchical bit-line architecture in which a plurality of pairs of sub bit lines are provided for a pair of main bit lines in order to, for example, reduce the number of sense amplifiers relative to the number of memory cells (see, for example, Japanese Laid-Open Patent Publication No. 6-349267).
In this type of DRAM, as schematically illustrated in FIG. 13, for example, four separate sub bit lines, e.g., sub bit lines /SBL20 through /SBL23, each having a length obtained by substantially equally diving the length of a main bit line, e.g., a main bit line /MBL2, are arranged in a main memory array region MM. Each main bit line is connected to a sense amplifier (not shown) so that a signal read out from a memory cell is sense-amplified.
The sub bit lines and the main bit lines are arranged at the same pitch as that of memory cells (not shown). More specifically, as illustrated in FIG. 14 showing a section Y in FIG. 13, sub bit lines SBL00 through SBL03 . . . /SBLn0 through /SBLn3 and main bit lines MBL0 through /MBLn are provided between word lines WL0 (through WL255) and word-line backing lines WL0_M (through WL255_M). The sub bit lines are evenly spaced and the main bit lines are also evenly spaced. Each of the sub bit lines and an associated one of the main bit lines overlap when viewed from above.
In such a DRAM, a read-out voltage ΔV obtained when data is read out from a memory cell is represented as:ΔV={1/(1+Cb/Cs)}×VDD/2−Vnoisewhere Cb is the sum of parasitic capacitances of a main bit line and a sub bit line (bit-line load capacity), Cs is the storage capacity of a memory cell, VDD is a power supply voltage, and Vnoise is a signal voltage which is lost by coupling noise, for example.
As also shown in FIG. 14, if a parasitic capacitance between the main bit line MBL1 and other lines is taken as an example, the bit-line load capacity Cb is the sum of a side coupling capacitance Cc, an overlap capacitance Co and a fringe capacitance Cf, for example.
However, conventional semiconductor memory devices have drawbacks such as difficulty in stable operation due to a decrease in a read-out voltage ΔV caused by reduction in line pitch. That is, when the line pitch decreases, especially the side coupling capacitance Cc increases and, thereby, coupling noise also increases. The increase in side coupling capacitance Cc and/or coupling noise causes the read-out voltage ΔV to decrease. This phenomenon is particularly conspicuous for lines with relatively large lengths such as main bit lines in a hierarchical bit-line architecture as described above or bit lines having no hierarchical bit-line architecture.